As silicon integrated circuits continue to shrink, various changes in the materials and processes used need to be made. These changes are quite separate from modifications associated with ever finer photolithography. For example, polysilicon had long been used as the preferred material for forming the gate pedestal in an FET device. As long as devices were relatively large (critical dimension greater than 0.5 micron) the resistivity of polysilicon was low enough so that additional circuit lines such as the gate line in a DRAM could be made using the same polysilicon layer as was used for the formation of the gate.
Once the critical dimension dropped below about 0.5 microns, it was found that the resistance of gate lines of pure polysilicon was too high. As a result, the use of tungsten silicide as an overlay over the polysilicon was introduced. In the prior art the standard practice has been to follow the deposition of the tungsten silicide with deposition of a layer of silicon oxide. This combination of silicon oxide, tungsten silicide, and polysilicon is then heated to a temperature of about 900.degree. C. in order to reduce the resistivity of the tungsten silicide.
The critical dimension of integrated circuits is now about 0.25 microns, or less. One consequence of these reduced dimensions has been the appearance of a new problem that is illustrated schematically in FIG. 1. What is shown is a silicon substrate 11 on whose surface is a layer of gate oxide 13 between two regions 12 of field oxide (FOX). Polysilicon layer 14 was deposited over the gate oxide followed by tungsten silicide layer 15 and silicon oxide layer 17. After the heat treatment described above, it was found that the resistance of gate lines formed from this composite was too high as was the contact resistance between layers 14 and 15.
Careful cross-sectioning of the structure revealed the presence of star like defects at the interface between the tungsten silicide and the silicon oxide. These are shown schematically as Xs such as 16. It thus appeared that during the anneal process some sort of reaction was occurring between the silicon oxide and tungsten silicide thereby reducing the effective thickness of the latter as well as placing a non-conductive layer between polysilicon and tungsten silicide. The present invention teaches a method for using tungsten silicide in conjunction with polysilicon but without the introduction of the defect layer shown in FIG. 1.
Since, as will be seen, the present invention involves a relatively small, but nevertheless critical, departure from prior art practices, the patent literature was carefully searched to ascertain whether or not the present invention had been anticipated. While a number of references were found that teach variations of the prior art process described above, none that embody the exact process of the present invention were discovered.
Several of the references that were found were, however, considered to be of interest. For example, in U.S. Pat. No. 5,411,907, Yoo et al show a poly/WSi gate with an anneal at at least 850.degree. C. However, the anneal step takes place after the deposition of the top layer of silicon oxide. Less than 40 minutes of anneal time is recommended.
In U.S. Pat. No. 5,558,910, Telford et al., a specific process for depositing tungsten silicide is described in some detail and mention is made of annealing the film after its deposition. However, this anneal is not followed by the deposition of an overlayer of silicon oxide so the effect of a subsequently deposited layer of silicon oxide cannot be known. They perform their anneal at 900.degree. C. in N.sub.2 for 30 minutes to reduce resistivity and eliminate peeling.
In U.S. Pat. No. 5,393,685, Yoo uses an RTA at a temperature in excess of 1,000.degree. C. for 30 to 60 minutes. As with the later Yoo patent mentioned above, the top layer of silicon oxide is in place during the anneal.
In U.S. Pat. No. 5,384,285, Sitaram et al. show a poly gate with a transition metal that is annealed at 600 to 700.degree. C. to form a silicide layer while in U.S. Pat. No. 5,593,924, Apte shows a Ti silicide anneal at 600 to 900.degree. C. to lower the resistivity. In U.S. Pat. No. 5,389,575 Chin et al. show a poly/silicide (e.g., TiSi or WSi) gate which is ion implanted with N.sub.2 to reduce resistivity while Miller (U.S. Pat. No. 4,322,453) shows a WSi anneal at temperatures up to 1000.degree. C. and higher. In U.S. Pat. No. 5,364,803, Lur et al. show a poly/TiN/WSi gate with exposure to F-atoms and an anneal to 850 to 1150.degree. C. for 10 to 60 minutes.